The explosion of intelligent IoT devices and connected vehicles, supported by a fast-growing communication and processing infrastructure, is creating an exponential demand for energy. If we want to properly use our limited resources, energy saving must be considered as our main innovation focus.
When it comes to IC design, we can distinguish the two following approaches:
– More speed, same power: achieve more computing power with the same energy budget
– Same speed, less power: achieve same level of performances with a drastic power consumption reduction
System-on-Chip architects and designers are now playing in this new technical paradigm and have to adopt innovative technologies and methodologies to reach their SoC PPA targets.
The webinar will start with an overview of the multidimensional challenges faced by IC design teams to enable energy-efficient SoC for heterogenous product profiles.
During this webinar, SoC architects, designers and project leaders involved in energy-efficient SoC designs will go through the following agenda:
- Process selection to build an energy-efficient device while ensuring high performance and high reliability
- Discover how a turnkey, fully integrated on-chip solution can bring unexpected PPA figures
- Check the methodology required to enable a smoot and seamless adoption of this innovative solution
This webinar will be held several times:
– For EU Time zone: October 1st
– For US Time zone: October 3rd
A session in Mandarin is planned on October 17th. Register to the Mandarin session by following this link.
For any other information on these webinars, you can contact Aurélie Descombes, Communication Manager.