Grenoble, France – May 29th, 2020
Battery-operated IoT devices must handle increasingly complex low-power schemes to ensure they can demonstrate high power-efficiency during sleep and operation modes.
Embedded power management is a critical functionality that controls and sequences the way the energy is distributed to each block in the circuit.
However, it requires an in-depth and transversal technical expertise from architecture to design, and can drastically slow down the conventional design cycle and increase the risk of silicon failure.
Leveraging our state-of-the-art IP portfolio and unique expertise in power network architecture, we have conceived SPIDER, a turnkey platform to accelerate the design of energy efficient power management systems. Seamlessly customizable to any application requirements and scalable to any SoC complexity, SPIDER brings together:
- Customizable analog & mixed-signal power management IPs: low-leakage and low quiescent voltage regulators, oscillators and power gating IPs, which are tailored to maximize energy efficiency in both sleep and active modes. They are built to work together and can easily be configured to match any application requirements.
- MAESTRO, a CPU-less power controller combining high configurability and ultra-low power consumption that works hand-in-hand with the power management IP family. It controls power mode sequencing and seamlessly manages retention, power gating and isolation strategies. MAESTRO is delivered as a configurable RTL IP that makes it compatible with any process node and scalable to any SoC architecture.
- PowerStudio, system-level utilities for fast power architecture, design and integration. Compatible with any process node and already pre-configured with the IP portfolio, it provides a single cockpit to build a coherent power network within the application’s constraints. From early power architecture exploration to RTL/UPF low-power flow enablement, when combined with MAESTRO, PowerStudio standardizes and accelerates power management design flow.
SPIDER platform provides a unique solution in the market and helps fabless companies to:
- Accelerate their time-to-market by designing a power management system in weeks, not months. SoC performances and PPA results can be assessed in days, not weeks
- Achieve ultimate energy efficiency with a state-of-the-art IP portfolio enabling innovative power management techniques
- Embed more functionalities with a customizable platform scalable to any SoC complexity
- Secure their silicon with a standardized and predictable power management flow
SPIDER is currently being used to enable ULP MCU and IoT tape-outs in 65/55 nm, 40 nm and 22 nm low-power process nodes (including FD-SOI and bulk technologies) and will soon be extended to FinFet.
Design an energy efficient power management system in weeks, not months. Do more, with less energy.