Category: Technical papers

Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824, June 2010
G. Depeyrot, F. Poullet and B. Dumas

Keywords: Verilog-A, compact model, SPICE Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), the Verilog-AMS hardware description language includes extensions dedicated to compact modeling, as a …

Guidelines for Verilog-A Compact Model Coding
Nanotech 2010 Vol. 2, pp. 821-824, June 2010
G. Depeyrot, F. Poullet and B. Dumas
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Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
C.Domingues
June 2010 GSA Forum

Smart electric meters are fundamental to the successful deployment of smart grid technology, as they improve grid reliability and user consumption control and reduce electricity theft. The variety of consumers’ emerging needs requires a much wider offering of energy metering systems-on-chip (SOCs), paving the way for more fabless companies to enter the energy measurement field. …

Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
C.Domingues
June 2010 GSA Forum
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Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods
A.BONZO

Introduction Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The methodology traditionally used in the industry to benchmark Standard Cell Libraries is the so- called “cell-by-cell” approach. It consists in taking one or two basic cells, such as a NAND2 …

Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods
A.BONZO
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Performance of high resolution analog functions embedded into a SoC guaranteed by the Three-Noise-Path method
F.ESPALIEU

Introduction System-on-Chip (SoC) integrators have to put in place appropriate verifications in order to guarantee performance of analog Virtual Components (ViCs), also called IP blocks, once integrated into the SoC. Such performances may be affected by various kinds of noise and the most critical issue in integrating analog functions is then to assess potential noise …

Performance of high resolution analog functions embedded into a SoC guaranteed by the Three-Noise-Path method
F.ESPALIEU
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Application hardware simulation to optimize system functions
ICCAD 2009 – China
N. Dufayard, H.Kuo, G.Depeyrot

Introduction Full-chip simulations are very quickly limited by excessive simulation time as well as by the availability of appropriate models. In the same way, simulation of a system cannot be effectively performed at the most accurate level both because it requires too much simulation time and because multi-domain systems cannot be accurately modeled using a …

Application hardware simulation to optimize system functions
ICCAD 2009 – China
N. Dufayard, H.Kuo, G.Depeyrot
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Selecting an embedded MCU: How to avoid evaluation trap?
IP-ESC’09 Conference – Grenoble, France
D.Maurer, A.Descombes

Abstract The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances. In this article, we will detail how to …

Selecting an embedded MCU: How to avoid evaluation trap?
IP-ESC’09 Conference – Grenoble, France
D.Maurer, A.Descombes
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Verification of Mixed Signal System Design accelerated by a new Diagnostic Tool-Kit
ASIM 20. Symposium Simulationstechnik Cottbus, Germany
D.Dammers, F.Tissafi Drissi, M.Giroud, D.Schollän, L. M.Voßkämper

Abstract Time-to-market is still required to decrease in state-of-the-art design processes. Reli- able verification of complete mixed-signal systems, i.e. logic and mixed signal electronics and systems with their attached peripherals, such as sensors and actuators, is needed to be performed quickly to fit in the enhanced design process. While the verification of the logic part, …

Verification of Mixed Signal System Design accelerated by a new Diagnostic Tool-Kit
ASIM 20. Symposium Simulationstechnik Cottbus, Germany
D.Dammers, F.Tissafi Drissi, M.Giroud, D.Schollän, L. M.Voßkämper
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Mixed Signal System Design Verification Accelerated With Detector-Based Diagnostic Method
BMAS – 2009 IEEE International Behavioral Modeling and Simulation Conference, San Jose, California, USA
D.Dammers, C.Domingues, D.Schollän, L.M.Voßkämper

Abstract Mixed-signal simulation of complete systems, i.e. pure ana- log/digital systems or electronics with its attached peripher- als, such as sensor and actuator systems, already have a firm place in today’s design process. While the digital part veri- fication has gained a speed increase through the use of Ac- cellera’s Property Specification Language (PSL), the …

Mixed Signal System Design Verification Accelerated With Detector-Based Diagnostic Method
BMAS – 2009 IEEE International Behavioral Modeling and Simulation Conference, San Jose, California, USA
D.Dammers, C.Domingues, D.Schollän, L.M.Voßkämper
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Accelerating Mixed Signal System Design Verification using New Diagnostic Method
ASIM – STS/GMMS Workshop, Dresden, Germany
D.Dammers, D.Schollän, L.M.Voßkämper

Abstract The mixed-signal simulation of complete systems, i.e. the electronics with its attached peripherals, such as sensors and actuators, already has a firm place in today’s design process. While the verification of the digital part, mostly implemented in Verilog and VHDL, has gained a speed increase through the use of Accellera’s Property Specification Language PSL, …

Accelerating Mixed Signal System Design Verification using New Diagnostic Method
ASIM – STS/GMMS Workshop, Dresden, Germany
D.Dammers, D.Schollän, L.M.Voßkämper
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Approach for modeling and evaluation of an actuator model for the positioning of read-/write heads in hard disk drives
Multi-Nature Systems (MNS), Ulm, Germany
T.Wiegand, D.Peters, St.Paul, R.Laur, R.Rosing, A.Richardson, B.Vigna, L.Voßkämper

Kurzfassung In diesem Beitrag wird die Modellierung und die Modelloptimierung eines Mikroaktors, der zur Positionierung von Lese-/Schreibköpfen in Festplatten entworfen wurde präsentiert. Zur Modellierung wurde die Verhaltensbe- schreibungssprache VHDL-AMS verwendet. Die Simulation wurde mit dem Verhaltenssimulator SMASH der Firma Dolphin Integration durchgeführt. Zur simulationsgestützten Modelloptimierung wurde das am ITEM ent- wickelte modelbasierte Designoptimierungssystem MODOS eingesetzt. …

Approach for modeling and evaluation of an actuator model for the positioning of read-/write heads in hard disk drives
Multi-Nature Systems (MNS), Ulm, Germany
T.Wiegand, D.Peters, St.Paul, R.Laur, R.Rosing, A.Richardson, B.Vigna, L.Voßkämper
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