Technical papers

Worldwide concerns of climate change and oil supply have triggered great interest in the electric vehicle (EV) and hybrid EV (HEV) segment of the automotive market. This rapid growth segment is also stimulated by the development of rechargeable batteries. As these “green” vehicles are powered by high-voltage (HV) battery packs consisting of hundreds of series-connected […]

Power efficiency in mobile audio headphone applications Paul Giletti A key for the success of mobile audio resides in power consumption reduction, as the battery must handle more applications and last a longer time. Regarding the analog audio, referred to as the audio CODEC where specifications mainly focus on the stereo playback mode, quiescent power

Reducing Power Consumption of microcontroller sub-systems using a Cache Controller Olivier Montfort Introduction Strong market requirements for decreasing the power consumption of embedded systems and increasing complexity of systems-on-chip require innovative solutions addressing such needs. In microcontrollers systems using memories like Flash, OTP, EPROM or EEPROM, the memories can consume a large part of the

Keywords: Verilog-A, compact model, SPICE Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), the Verilog-AMS hardware description language includes extensions dedicated to compact modeling, as a

Smart electric meters are fundamental to the successful deployment of smart grid technology, as they improve grid reliability and user consumption control and reduce electricity theft. The variety of consumers’ emerging needs requires a much wider offering of energy metering systems-on-chip (SOCs), paving the way for more fabless companies to enter the energy measurement field.

Introduction Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The methodology traditionally used in the industry to benchmark Standard Cell Libraries is the so- called “cell-by-cell” approach. It consists in taking one or two basic cells, such as a NAND2

Introduction System-on-Chip (SoC) integrators have to put in place appropriate verifications in order to guarantee performance of analog Virtual Components (ViCs), also called IP blocks, once integrated into the SoC. Such performances may be affected by various kinds of noise and the most critical issue in integrating analog functions is then to assess potential noise

Introduction Full-chip simulations are very quickly limited by excessive simulation time as well as by the availability of appropriate models. In the same way, simulation of a system cannot be effectively performed at the most accurate level both because it requires too much simulation time and because multi-domain systems cannot be accurately modeled using a

Abstract The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances. In this article, we will detail how to

Abstract Time-to-market is still required to decrease in state-of-the-art design processes. Reli- able verification of complete mixed-signal systems, i.e. logic and mixed signal electronics and systems with their attached peripherals, such as sensors and actuators, is needed to be performed quickly to fit in the enhanced design process. While the verification of the logic part,